Principal Functional Verification Engineer

Principal Functional Verification Engineer

Role

As a Functional Verification Principal Engineer, you will be interfacing with architecture, design, physical implementation and software teams in order to make sure that the systems are performing to the highest level.

Your work will involve high-level modelling, UVM, HW/SW Co-Debug, Simulation Acceleration support.

Key Responsibilities

• Reading and analysing the system requirements and architecture requirement documents.
• Developing detailed Test and Coverage plans based on the Architecture and Micro-architecture.
• Developing Verification Methodology, ensuring scalability and portability across environments.
• Developing Verification environment development and maintenance in System Verilog/UVM/System C/C++, including all the respective components such as Stimulus, Checkers, Assertions, Trackers, and Coverage.
• Executing Verification Plans, including Design Bring-up, DV environment Bring-up, Regressions and Debug of the test failures.
• Using the standard tools and flows of the verification process (Simulators, Coverage Analyzers, Unix, Continuous Integration, Bug Tracking, …).
• Creating and executing test cases to verify the functionality, performance, and robustness in embedded C and SV.
• Identifying, isolating, and debugging issues found during verification, leveraging simulation and debugging tools to root‑cause failures and drive resolution with design and architecture teams.
• Working closely with cross‑functional teams to achieve verification closure, conducting coverage analysis, bug tracking, and regression testing to ensure the quality and completeness of verification activities.
• Organizing work and deliverables between skills, internal and external teams.
• Mentoring and training the next generation of verification engineers.
• Coordinating functional verification teams.

Required Skills and Experience

• Master Degree in a relevant field.
• Minimum 15 years of experience in verification of complex So C or IP.
• Experience in System Verilog/UVM.
• Experience in System C/C++.
• Experience in Formal Verification and UPF.
• Experience in HW–SW co‑verification and simulation.
• Some previous experience in firmware‑based verification is a good to have.
• Knowledge of scripting languages such as Bash, Perl, Python.
• Experience using verification management tools.
• Strong debugging and problem‑solving skills, with the ability to effectively analyze and resolve complex verification issues.
• Good level of English, both written and spoken, is mandatory.

Preferred Qualifications

• Experience in firmware‑based verification.
• Insights of NOC and other IPs or standard peripherals such as PCIe, DDR, HBM.
• Team player, able to work with multiple cultures both on site and remotely.
• Autonomous and flexible is mandatory.
• Strong leadership and communication abilities.

What We Offer

• Join an innovative team and experience company growth.
• We believe in investing in our employees and providing them with opportunities to grow and develop their careers.
• Enjoy a hybrid work environment.
• We offer flexible scheduling.
• We provide a remuneration that values your experience.
• The position will be based in Rome.

We are a diverse and inclusive team.

We foster a work environment where everyone feels valued, respected, and empowered to reach their full potential – regardless of race, gender, ethnicity, sexual orientation, or gender identity.

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