Principal Physical Digital Design Engineer

About Fondazione Chips-IT

The Foundation “Italian Center for the Design of Semiconductor Integrated Circuits,” also known as the Chips-IT Foundation, is a nonprofit research and technology organization under the supervision of the Ministries of Industry.

The Foundation is Italy’s first RTO (Research and Technology Organization) vertically focused on semiconductor research and stands as a center of excellence in frontier research on semiconductor design, as well as a pivotal center of the Italian semiconductor ecosystem and expertise.

• Missions Of The Foundation
• Promote the design and development of integrated circuits
• Strengthen the system of professional training in the field of microelectronics
• Ensure the establishment of a network of universities, research centers and enterprises that fosters innovation and technology transfer in the field
• Posizione

The Chips-IT Foundation is expanding its microelectronics design team and is seeking a highly experienced Principal Physical Design Engineer to play a key technical leadership role in advanced System-on-Chic (So C) development programs.

The position will contribute to cutting-edge R&D activities, working closely with architecture, RTL, verification, and technology teams in a state-of-the-art microelectronics design environment.

The Principal Physical Design Engineer will be responsible for leading and executing complex digital design flows for advanced semiconductor nodes.

The role requires deep hands-on expertise across the full physical implementation lifecycle, from netlist handoff through place & route, signoff, and tape-out, while also providing technical mentorship and driving best practices within the design team.

The work can be carried out either in Pavia or in Bologna.

Key Responsibilities

• Lead and execute end-to-end physical design flows for complex So Cs and IP blocks, from RTL handoff to GDSII.
• Collaborate closely with RTL, verification, DFT, and architecture teams to resolve design and implementation issues.
• Work with PDKs and technology teams to ensure correct usage of advanced-node design rules and constraints.
• Develop, document, and improve physical design methodologies, scripts, and automation flows.
• Mentor junior engineers and provide technical leadership across physical design activities.
• Requisiti
• Master’s degree (or Ph D) in Electrical Engineering, Computer Engineering, or a related field.
• Extensive hands-on experience in physical design for advanced technology nodes (e. g., 16nm and below).
• Strong expertise with industry-standard EDA tools (Cadence, Synopsys, Siemens).
• Solid understanding of semiconductor fabrication processes and foundry design requirements.
• Proficiency in Tcl, Python, or Perl for flow automation and methodology development.
• Experience supporting multiple tape-outs in advanced nodes.
• Altre Informazioni

WHAT WE OFFER

• Competitive compensation and contract type, to be negotiated based on qualifications and experience
• Possibility to enter into a Ph D conjugating your job with a research program that will grant you the Ph D title.
• Lunch tickets
• Private health care coverage depending on your role and contract
• Structured growth path, with ongoing access to training and updates
• Networking opportunities with industry-leading professionals
• International environment
• Hybrid work policy
• Tax deductions: Candidates from abroad, comprising Italian citizens, who have carried scientific research activity abroad and meet specific requirements, may be entitled to a taxable income deduction up to 90% for a period of 6 to 13 years

In conformità con le normative vigenti, il range retributivo lordo annuo previsto per questa posizione è compreso tra Euro 25.000,00 e 55.000,00.

L’ampiezza del range è finalizzata a valutare candidature con diversi livelli di seniority; l’offerta finale sarà strettamente commisurata all’effettiva esperienza e alle competenze del candidato, e sarà integrata dai benefit aziendali previsti per il ruolo.