Head of Silicon in Parma

Location: Italy / Hybrid -- Employment: Full-time - Compensation: €85,000–€100,000 gross annual salary (RAL), depending on experience - Equity: Stock options / equity participation available

About Daidalos

Daidalos is building a new generation of AI accelerator IP designed to bring advanced and agentic AI directly to the edge.

Our architecture addresses one of the key bottlenecks of modern AI systems: the movement of data between memory and compute.

By rethinking how neural-network workloads are mapped onto hardware, we aim to deliver high performance with significantly lower memory bandwidth, power consumption and system complexity.

We are moving from FPGA validation toward our first silicon implementations and are looking for a

Head of Silicon to lead this transition.

The Role

We are looking for an experienced semiconductor leader who can take ownership of the silicon development process, from architecture handoff to tape-out and silicon bring-up.

You will work directly with the founders and technical team, translating our AI accelerator architecture into a manufacturable, reliable and high-performance ASIC.

This is a hands-on leadership role.

At this stage, we are looking for someone who is comfortable both making architectural decisions and getting deeply involved in implementation, verification and tape-out execution.

Because our technology sits at the intersection of

AI algorithms and semiconductor architecture , the ideal candidate must be able to understand not only how to build a chip, but also how neural networks behave computationally and how AI workloads should influence hardware design decisions.

• What You Will Own
• Lead the end-to-end

ASIC development process , from RTL to GDSII and tape-out.

• Define the silicon implementation roadmap, methodology and execution plan.
• Drive synthesis, timing closure, physical design, power and area optimization.
• Own sign-off activities including STA, DRC, LVS, power integrity and related verification flows.
• Coordinate RTL, verification, backend, packaging, foundry and external engineering partners.
• Work closely with the architecture and AI teams to translate algorithmic and performance requirements into silicon constraints and implementation choices.
• Evaluate architectural trade-offs related to compute, memory bandwidth, data movement, latency, power and area.
• Select and manage EDA tools, semiconductor IP blocks and external suppliers.
• Drive design reviews and ensure technical readiness ahead of tape-out.
• Support first-silicon bring-up, characterization and debugging.
• Help define the long-term silicon roadmap.
• Build and progressively lead the silicon engineering organization as the company scales.
• What We Are Looking For

10+ years of experience in ASIC / So C development , preferably with direct ownership of complex chips, or a Ph D in a relevant field followed by at least 2 years of hands‑on industrial experience in ASIC / So C design and implementation .

• At least one successful tape‑out , with direct involvement in the development and implementation process.
• Strong understanding of the complete

RTL-to-GDSII flow .

• Deep experience in areas such as synthesis, STA, physical design, power optimization and silicon sign‑off.
• Experience working with advanced semiconductor process nodes;

Fin FET tape‑out experience is highly valued .

• Strong understanding of neural networks, AI algorithms and their computational characteristics .
• Familiarity with major AI architectures and workloads, including

CNNs, Transformers and LLMs .

• Understanding of concepts such as quantization, sparsity, matrix operations, memory bandwidth, data movement and compute efficiency .
• Ability to work across the boundary between

AI algorithms and hardware architecture , translating model‑level requirements into efficient silicon implementations.

• Ability to navigate trade‑offs between performance, power, area, memory bandwidth, schedule and cost.
• Experience working with foundries, EDA vendors and semiconductor IP providers.
• Strong technical judgment and the ability to operate in a fast‑moving early‑stage environment.
• Fluent professional English.

Experience with

AI accelerators, NPUs, GPUs, tensor processors, high‑performance compute architectures or advanced memory subsystems is a strong plus.

Why Join Daidalos

This is an opportunity to join at the point where a new AI architecture becomes a chip.

You will have direct influence over the silicon strategy, implementation methodology and technical organization of the company.

Rather than joining a mature semiconductor organization to optimize an existing product line, you will help define how a new architecture is translated into silicon from the ground up.

You will work closely with the founders, technical team and an international ecosystem of semiconductor partners, foundries, EDA providers, accelerators and research institutions.

Most importantly, you will have the opportunity to take a new AI architecture from FPGA to first silicon — and help build the semiconductor team around it.

Compensation

€85,000–€100,000 RAL , depending on seniority, technical background and experience.

The compensation package can also include stock options / equity participation , reflecting the level of responsibility and long‑term impact of the role.

#J-18808-Ljbffr